Trent Josephsen's Resume

Nathan “Trent” Josephsen

(443) 770-2381
trent@josephsen.us

Experience

Automated circuit bit error rate and parametric yield simulation using C, Python, and Cadence SKILL
Spearheaded gate library development, wrote and maintained scripts and documentation for logic gate characterization, and trained new designers
Developed a new methodology for phase assignment and single-to-dual-rail conversion in pulse-conserving superconducting circuits
Created a graph-based test pattern generator to exhaustively exercise arbitrary AC powered SFQ logic circuits in minimal simulation time
Designed and implemented a Python- and MongoDB-based lab automation framework for concurrent experiments, with automated tracking of metadata in an object-oriented database
Managed lab inventory, established safety procedures and oversaw the installation of a new cryostat
Diagnosed and implemented fixes for lab equipment problems and data hygiene issues and implemented weekly data reviews
Performed design of experiments and data analysis for process control structures in imec's 300 mm NbTiN superconducting pilot process
Successfully tested the first superconducting 50nm NbTiN wires and NbTiN-αSi-NbTiN Josephson junctions
Onboarded and trained new engineers and interns in lab and design teams
Established version control practices and administered the imec USA GitHub
Liased with software vendors and IT service providers

Designed groundbreaking digital circuits in an experimental superconducting logic family, Reciprocal Quantum Logic (RQL)
Created the gate level design, layout, and test plan for a register file chip that was the most complex RQL circuit ever successfully tested at the time
Designed a scalable circuit and test procedure capable of finding process faults via digital test
Parallelized and streamlined a yield calculation and circuit optimization tool written in C
Wrote and maintained an in-house timing and rule-checking tool, which greatly reduced time spent on manual circuit verification, in VHDL
Invented a method to efficiently compute a steady-state AC operating point for superconducting circuits, enabling highly accurate circuit verification
Developed a new timing engine, capable of verifying larger (CPU sized) designs, driven by an industry-standard Tcl interface, in modern C++
Regularly onboarded new designers and wrote internal documentation for the RQL technology

Programming, functional and object-oriented software architecture: C, Python, Perl, Rust, bash, Cadence SKILL
Databases: SQLite3 and MongoDB
Digital hardware design: ModelSim, Cadence Xcelium, VHDL and Verilog
Revision control: Git, SVN, Perforce
Electronic design, modeling, simulation, gate library characterization and optmization: Cadence Virtuoso, SPICE & Spectre
Other software: Linux (many varieties), Visio, make, cmake

Q. Herr, T. Josephsen, A. Herr; "Superconducting Pulse-Conserving Logic and Josephson-SRAM." Applied Physics Letters 122, 182604 (2023). doi:10.1063/5.0148235
Q. Herr, A. Braun, A. Brownfield, E. Rudman, D. Dosch, T. Josephsen, A. Herr; "Measurement and Data-Assisted Simulation of Bit Error Rate in RQL Circuits." Superconductor Science and Technology 35, 025017 (2022). doi:10.1088/1361-6668/ac45a1
S. Iraci et al.; "Two Metal Level Semi-Damascene Interconnects for Superconducting Digital Logic." 2024 IEEE International Interconnect Technology Conference (IITC), San Jose, CA, USA, 2024, pp. 1-3. doi: 10.1109/IITC61274.2024.10732342
A. Pokhrel et al.; "NbTiN Based Two-Metal Level Semi-Damascene Interconnects, Josephson Junctions and Capacitors for Superconducting Digital Logic," 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024, pp. 1-4. doi:10.1109/IEDM50854.2024.10873563
A. Pokhrel et al.; "Towards Enabling Two Metal Level Semi-Damascene Interconnects for Superconducting Digital Logic: Fabrication, Characterization and Electrical Measurements of Superconducting NbxTi(1-x)N." 2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM), Dresden, Germany, 2023, pp. 1-3. doi:10.1109/IITC/MAM57687.2023.10154725
A. Herr et al.; "Scaling NbTiN-based ac-powered Josephson digital to 400M devices/cm²." Preprint (2023). doi:10.48550/arXiv.2303.16792